1. Field of the Invention
The present invention relates to a memory, system, and more particularly to an apparatus and method for using a partially functional dynamic random access memory(DRAM) on a system board to compensate for the problem of bit defect, to improve the traditional fail bit memory scheme, to simplify the mapping between external address and fail bit address, and to provide a way to adapt the memory system for changing situation, such as memory device aging or abnormality.
2. Description of the Prior Art
Memory device is one of the most important devices used in digital electronic systems such as computers and peripherals. While the speed of central processing unit(CPU) increases continuously and the function of system becomes more complicated, there demands a memory device with high density. Unfortunately as the density of memory device increases, bit defect due to the limit of fabrication process in the semiconductor industry will render the memory device useless.
A number of techniques have been designed to compensate for the problem of bit defect. One of the well-known techniques in the prior art is redundancy scheme, which provides extra rows and columns on chip to replace defective bits in rows or columns. There is an inherent limitation that a redundant row/column can only replace a defective row/column or a single bit. At the worst, there will run short of extra rows and columns to replace all of the defective bits when those defective bits are distributed widely.
Another scheme as shown in FIG. 1 in the prior art is disclosed in U.S. Pat. No. 5,270,974 "Monolithic Fail Bit Memory" by Reddy, who adds a fail bit memory 11 to each main memory 12 chip and the defective bits in the main memory are replaced by bits in the fail bit memory using a programmable logic array(PLA) 13. If there is a match between the external address and an internal location in the PLA 13, the PLA outputs a flag 14 and a fail bit address 15 which are used to disable the main array 12 access and to enable access to the fail bit memory 11.
The fail bit memory scheme described above could be utilized preferably in chip level to overcome the disadvantage of the redundancy scheme, but has some drawbacks when practicing in board level, although the inventor suggests that the scheme could be expanded for use to create a fully functional memory board using partially functional memory chips. The first difficulty when practicing in board level is the complicated mapping method, which translates an external address to a fail bit address to access the fail bit memory 11, and the mapping is implemented by fusing the PLA 13 permanently, making it difficult to change the contents of the PLA later on; secondly the fail bit memory 11 is accessed directly through a global address containing row address and column address which demand additionally a decode logic to combine the two address when the fail bit memory is other than a dynamic RAM(DRAM); lastly defective bits could be introduced in any stage after the chip is completed such as in package process, in stress burn-in test, or due to device aging. The method based on the fail bit memory scheme described above could not be adapted for any later fail bit change, because there lacks a method and means to modify the contents of the fail bit memory 11 and the PLA 13.